The present invention relates to a semiconductor memory device, and in particular, an improvement of a redundancy technique for a DRAM in which address fuses are arranged in a form of a plurality of stages of row.
In the technical field of a semiconductor device, elements to be incorporated into a semiconductor chip have been formed to have a smaller size, thus increasing the number of elements incorporated into one semiconductor chip. This has been accompanied by an increase in the number of defects in the elements. Furthermore, due to dusts or impurities fallen onto a portion of the memory cell array of the semiconductor chip, a large size of defect has occurred in the elements on the memory cell array portion. These element or elements are referred to as defective element or elements hereinafter.
However, the yield was low just after such smaller semiconductor elements had been developed or at the beginning of their mass production. To solve this problem, a technique for providing a redundant element control circuit has been proposed, and put to practical use (hereinafter this technique will be referred to a redundancy technique). In the redundancy technique, redundant elements are prepared on the supposition that the semiconductor device has defective elements. To be more specific, if a defective element is detected in a manufactured memory cell array, a redundant element is used instead of the defective element. That is, when an input address signal for designating the defective element is inputted, a redundant element is selected instead of the defective element.
Such a technique is the above-mentioned redundancy technique. By virtue of the redundancy technique, even if a semiconductor device includes a defective element, it can be used as a non-defective semiconductor device by employing a redundant element instead of the defective element.
The defective elements may cause in a row (word line). The defective elements may cause in a column (bit line pair). The defective elements may cause in a plurality of rows (word lines). The defective elements may cause in a plurality of columns (bit line pairs). Accordingly, the redundant element or elements mean element or elements contained in a row (word line), element or elements contained in a column (bit line pair), element or elements contained in a plurality of rows (word lines), or element or elements contained in a plurality of columns (bit line pairs). That is, the redundant element or elements mean element or elements contained in a row (word line) as a unit, element or elements contained in a column (bit line pair) as a unit, element or elements contained in a plurality of rows (word lines) as a unit, or element or elements contained in a plurality of columns (bit line pairs) as a unit.
The size of the semiconductor chip is slightly increased when the redundancy technology is incorporated thereinto. However, the yield is greatly improved, since as explained above, a semiconductor device is employed as a non-defective device even if it includes a defective element.
FIG. 9 illustrates a redundant element control circuit. A plurality of the redundant element control circuits are provided for the respective redundant elements. Addresses are programmed to each of redundant element control circuit to designate a corresponding redundant element. Thus, when an input address signal is inputted to the redundant element control circuits, a corresponding redundant element control circuit is selected and activated in response to the input address signal to select the corresponding redundant element.
The redundant element control circuit 6 comprises a fuse latch circuit group 4 and a comparator 5 which will be explained later with reference to FIG. 12. The fuse latch circuit group 4 includes a plurality of fuse latch circuits, which are required to select an associated redundant element. Each of the fuse latch circuits is illustrated in FIG. 10, and thus will be explained with reference thereto as follows:
The fuse latch circuit, as shown in FIG. 10, comprises a PMOS transistor Tr1, an NMOS transistor Tr2, an inverter INV1, an inverter INV2, a transmission gate Tr3, a transmission gate Tr4, and an address fuse 3. The transmission gate Tr3 is constituted by a parallel circuit comprising a PMOS transistor and an NMOS transistor. Also, the transmission gate Tr4 is constituted by a parallel circuit comprising a PMOS transistor and an NMOS transistor.
An initializing signal X is inputted to the gate of the PMOS transistor Tr1, and an initializing signal Y is inputted to the gate of the NMOS transistor Tr2. The source of the PMOS transistor Tr1 is connected to power supply potential, and the drain of the PMOS transistor Tr1 is connected to the drain of the NMOS transistor Tr2. The source of the NMOS transistor Tr2 is connected to an address fuse FAi, and then connected to ground potential by the address fuse FAi. An input terminal of the inverter INV1 is connected to a common drain node of the transistors Tr1 and Tr2. Also, an output terminal of the inverter INV2 is connected to the common drain node of the transistors Tr1 and Tr2. An output terminal of the inverter INV1 is connected to an input terminal of the inverter INV2.
The gate of the PMOS transistor of the transmission gate Tr3 and the gate of the NMOS transistor of the transmission gate Tr4 are also connected to the common drain node of the transistors Tr1 and Tr2. The gate of the NMOS transistor of the transmission gate Tr3 is connected to the output terminal of the inverter INV1. To be more specific, the gate of the PMOS transistor of the transmission gate Tr3 and the gate of the NMOS transistor of the transmission gate Tr4 are connected to the common drain node of the transistors Tr1 and Tr2, and the gate of the NMOS transistor of the transmission gate Tr3 and the gate of the PMOS transistor of the transmission gate Tr4 are connected to the output terminal of the inverter INV1.
An address ADD&lt;i&gt; is inputted to the transmission gate Tr3 from an address line of an address bus through a local line, and an address /ADD&lt;i&gt; is inputted to the transmission gate Tr4 from another address line of the address bus through another local line. The character "/" represents a logical inversion signal (complementary signal). Address ADD&lt;i&gt; is outputted from the transmission gate Tr3 as an output FOUT&lt;i&gt;, or address /ADD&lt;i&gt; is outputted from the transmission gate Tr4 as an output FOUT&lt;i&gt;.
In the fuse latch circuit 4, when power is supplied, the initializing signals X and Y, which are illustrated in FIG. 11, are inputted to the gate of the PMOS transistor Tr1 and the gate of the NMOS transistor Tr2, respectively, and the fuse latch circuit 4 is thus initialized. When the input address signal is changed, ADD&lt;i&gt; is outputted from the transmission gate Tr3 or /ADD&lt;i&gt; is outputted from the transmission gate Tr4, as the output FOUT&lt;i&gt; of the fuse latch circuit 4. Whether ADD&lt;i&gt; is outputted or /ADD&lt;i&gt; is outputted depends on whether or not the fuse FAi is cut.
The comparator 5, as shown in FIG. 12, comprises a NAND circuit on its input side and a NOT circuit on its output side. The NOT circuit is series-connected to the NAND circuit. When the number of addresses required to select a redundant element is n+1, the NAND circuit receives FOUT&lt;0&gt; to FOUT&lt;n&gt;. When all FOUT&lt;0&gt; to FOUT&lt;n&gt; are at 1 level, the comparator 5 generates a redundant element enabling signal ENABLE, to thereby activate an associated redundant element. When the associated redundant element is activated, a memory element connected thereto is activated.
As explained above, the redundant element control circuits each having a fuse latch circuit group 4 and a comparator 5 are provided for the respective redundant elements. The fuse latch circuit group 4 comprises a plurality of fuse latch circuits, which are required to select an associated redundant element. Each of the fuse latch circuits includes an address fuse FA (FIG. 8), which is associated with an address to be programmed thereto. Therefore, if the number of redundant elements is increased, the total number of address fuses is also increased, and thus the address fuses cannot be arranged in one row. Therefore, in the conventional semiconductor memory device, the address fuses are arranged in a form of a plurality of fuse rows (stages), e.g., two fuse rows 1 and 1' (two stages) as shown in FIG. 8. Address lines of an address bus are provided in a region between adjacent two of the fuse rows, e.g., in a region between the fuse rows 1 and 1' as shown in FIG. 8.
In the conventional semiconductor memory device, when the address fuses are arranged in a form of a plurality of fuse rows (stages), e.g., two fuse rows, a plurality of sets of the address fuses, which are respectively associated with the redundant elements, are divided into two groups (two rows), and each of the address fuse sets is provided in any one of two rows, as shown in FIG. 13. The address fuses of each address fuse set are associated with addresses for designating a corresponding redundant element. In the example of FIG. 13, a fuse set 2 (including fuses FA0, FA1, FA2 . . . FAn) associated with a redundant element is provided in a fuse row 1 (the first stage), and a fuse set 2' (including fuses FA0, FA1, FA2 . . . FAn) associated with another redundant element is provided in a fuse row 1' (the second stage). That is, a plurality of address fuses associated with the same address are arranged in both of the two fuse rows 1 and 1'.
In the conventional semiconductor memory device, two address lines are provided for the fuse rows 1 and 1', respectively, as shown in FIG. 14, in the case where it is difficult to provide a layout of local lines from an address line to the fuse latch circuits, e.g. 4n, of the redundant element control circuits. In other words, the memory device needs two address lines one of which is for the fuse row 1 and the other is for fuse row 1' (in the case where the input address signal is a complementary address signal, four address lines are needed two of which are for the fuse row 1 and the other two are for fuse row 1'). Address lines A0, A1, A2 . . . An (six address lines in the example shown in FIG. 14) are provided for the fuse row 1, and address lines A0, A1, A2 . . . An (six address lines in the example of FIG. 14) are provided for the fuse row 1'. Accordingly, in the example of FIG. 14, the two address lines are provided to each of the addresses, as a result of which the region occupied by the address lines is great, thus increasing the address line area on the semiconductor chip. Furthermore, the consumption of current for driving the address lines is large since the number of address lines is large. In addition, the capacitance of the address lines is increased, and thus the address transition speed is lowered, and as a result the speed of selection of a redundant element is also lowered, as long as the sizes of address drivers provided for driving the address lines are not increased.
Moreover, there is a case where as shown in FIG. 15, it is possible to provide a layout of the local lines from one address line to the fuse latch circuits of the redundant element control circuits, whose address fuses are arranged in the form of two rows 1 and 1'. In this case, the address lines A0, A1, A2 . . . An (six address lines in the example shown in FIG. 15) are provided between the two fuse rows 1 and 1', as common address lines. To be more specific, the common address lines are used commonly for both the fuse rows 1 and 1', and thus connected commonly, by the local lines, to the fuse latch circuits 4i of the redundant element control circuits on the sides of the fuse rows 1 and 1'. However, the local lines must be extended from the common address lines toward the fuses 1 and 1', respectively. They must have great lengths. As a result, the parasitic capacitance of the local lines connected to the address lines is increased, and thus the consumption of current for driving the address lines is also increased. Consequently, the transition speed of the input address signal is lowered, and that of selection of a redundant element is also lowered, as long as the sizes of the address drivers are not increased.